module alu_tb;
 
  reg clk;
  reg [31:0] busA, busB;
  reg [1:0] ALUctr;
 
  wire [31:0] Alu_out;
  initial begin
    clk = 0;   
    repeat (8) begin   //set clock 
      #5 clk = ~clk;
    end
  end
  // get  ALU  module
  alu dut(            
    .busA(busA),
    .busB(busB),
    .ALUctr(ALUctr),
    .Alu_out(Alu_out)
  );               
  parameter ADD=2'b00;
  parameter SUB=2'b01;
  parameter OR=2'b10;
  parameter AND=2'b11;  
  
  //check ALU_out correct or not 
   initial begin
    #5
    ALUctr = ADD;
    busA = $random;
    busB = $random;
    #10
    ALUctr = SUB;
    busA = $random;
    busB = $random;
    #10
    ALUctr = OR;
    busA = $random;
    busB = $random;
    #10
    ALUctr = AND;
    busA = $random;
    busB = $random;
   end    
  initial begin
    $dumpfile("ALU_wave.vcd");
    $dumpvars(0,alu_tb);
  end
endmodule